Semiconductor device including air gaps and method of fabricating the same

ABSTRACT

This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures, The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalis of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2012-0153806, filed on Dec. 26, 2012, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to a semiconductordevice, and more particularly, to a semiconductor device including airgaps and a method of fabricating the same.

2. Description of the Related Art

In general, a semiconductor device includes a second conductivestructure formed between a plurality of first conductive structures,wherein an insulation layer is interposed between the second conductivestructure and the first conductive structure. For example, the firstconductive structures may include a gate, a bit line, a metal wire,etc., and the second conductive structures may include a contact plug, astorage node contact plug, a bit line contact plug, a via, etc.

As the degree of integration of semiconductor devices is increased, aninterval between the first conductive structure and the secondconductive structure is gradually narrowed. For this reason, parasiticcapacitance between the first conductive structure and the secondconductive structure is increased, As the parasitic capacitance isincreased, the operating speed of the semiconductor device is decreasedand a refresh characteristic is deteriorated.

In order to reduce the parasitic capacitance, a method of lowering thedielectric constant of the insulation layer may be used. Insemiconductor devices, an insulation layer is chiefly made of siliconoxide or silicon nitride. A silicon oxide layer has a dielectricconstant of about 4, and a silicon nitride layer has a dielectricconstant of about 7.

A reduction of parasitic capacitance is limited because a silicon oxideor a silicon nitride still has a high dielectric constant. A materialhaving a relatively low dielectric constant has recently been developed,but the dielectric constant of the material may be not so low.

SUMMARY

Exemplary embodiments of the present invention are directed to providinga semiconductor device and a method of fabricating the same, which mayreduce parasitic capacitance between adjacent conductive structures.

In accordance with an exemplary embodiment of the present invention, amethod of fabricating a semiconductor device includes forming aplurality of bit line structures over a substrate; forming contact holesbetween the bit line structures; forming sacrificial spacers oversidewalls of the contact holes, forming first plugs recessed into therespective contact holes, forming air gaps by removing the sacrificialspacers, forming capping structures capping the air gaps while exposingtop surfaces of the first plugs, and forming second plugs over the firstplugs.

In accordance with another exemplary embodiment of the presentinvention, a method of fabricating a semiconductor device includesforming a plurality of bit line structures over a substrate; formingcontact holes between the bit line structures; forming sacrificialspacers on sidewalls of the contact holes; forming silicon plugsrecessed into the respective contact holes; forming air gaps by removingthe sacrificial spacers; forming capping structures capping the air gapswhile exposing top surfaces of the silicon plugs; forming ohmic contactlayers over the silicon plugs; and forming metal plugs over the ohmiccontact layers.

In accordance with still another exemplary embodiment of the presentinvention, a semiconductor device includes a plurality of bit linestructures formed over a substrate; storage node contact holes formed tohave sidewalls of the bit line structures exposed therethrough; siliconplugs recessed and formed in the respective storage node contact holes;air gaps formed between the sidewalis of the bit line structures and thesilicon plugs; capping layer patterns formed over the air gaps;passivation layers formed over the respective capping layer patterns andmetal plugs formed over the respective silicon plugs, wherein the airgaps are capped with the respective capping layer patterns andpassivatlon layers,

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view illustrating a portion of asemiconductor device in accordance with an embodiment of the presentinvention.

FIGS. 2A to 2K show cross-sectional views showing a method of forming asemiconductor device in accordance with an embodiment of the presentinvention.

FIGS. 3A and 3B illustrate comparative examples that are compared withembodiments of the present embodiment,

FIG. 4A shows memory cells of DRAM.

FIG. 4B is a cross-sectional view of the DRAM taken along line A-A′ ofFIG. 4A.

FIG. 4C is a cross-sectional view of the DRAM taken along line B-B′ ofFIG. 4A.

FIG. 5 is a schematic diagram of a memory card.

FIG. 6 is a block diagram of an electronic system.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

The drawings are not necessarily to scale and in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When a first layer is referred to as beingn a second layer or a substrate it not only refers to a case where thefirst layer is formed directly on the second layer or the substrate butalso a case where a third layer exists between the first layer and thesecond layer or the substrate.

FIG. 1 is a cross sectional view illustrating a portion of asemiconductor device in accordance with an embodiment of the presentinvention.

Referring to FIG. 1, semiconductor structures are formed over asubstrate 101. The semiconductor structure may include a plurality ofconductive structures. The conductive structures may include firstconductive structures 104 and second conductive structures 109. An airgap 110 may be formed between the first conductive structure 104 and thesecond conductive structure 109. A capping layer 111 and a passivationlayer 112 may be formed over the air gap 110.

Each of the first conductive structures 104 may include a firstconductive layer 102. The first conductive structure 104 may have astack structure including the first conductive layer 102 and a hard masklayer 103. The first conductive layer 102 may include asilicon-containing layer or a metal-containing layer. The firstconductive layer 102 may be formed by stacking the silicon-containinglayer and the metal-containing layer. The first conductive layer 102 mayinclude polysilicon, metal, metal nitride, metal silicide, or the like.The first conductive layer 102 may be formed by stacking a polysiliconlayer and a metal layer. The metal layer may include tungsten (W). Thehard mask layer 103 may include an insulating material, The hard masklayer 103 may include oxide or nitride. One of the first conductivestructure 104 and the second conductive structure 109 may have a linetype in which the conductive structure extends in one direction. Theother of the first conductive structure 104 and the second conductivestructure 109 may have a plug type. For example, the first conductivestructure 104 may be a structure having a line type, and the secondconductive structure 109 may be a structure having a plug type. Thefirst conductive structures 104 may be regularly arranged on thesubstrate 101 at regular intervals.

The second conductive structure 109 may include a second conductivelayer 106 recessed between the first conductive structures 104. Each ofthe second conductive structures 109 may have a stack structureincluding the second conductive layer 106, an ohmic contact layer 107,and a third conductive layer 108. The second conductive layer 106 mayinclude a silicon-containing layer. The second conductive layer 106 mayinclude a polysilicon layer. The third conductive layer 108 may includea metal-containing layer. The ohmic contact layer 107 may include metalsilicide, such as cobalt silicide. The third conductive layer 108 mayinclude metal, metal silicide, metal nitride, or the like. The thirdconductive layer 108 may have a stack structure including a barrierlayer and a metal layer. The barrier layer may include metal nitride.The third conductive layer 108 may include a material including titanium(Ti) or tungsten (W) as main ingredients.

The capping layer 111 may be of a type that caps the air gap 110. Thecapping layer 111 may include the oxide of the second conductive layer106. In particular, the capping layer 111 may include the plasma oxideof the second conductive layer 106. The capping layer 111 may includesilicon oxide.

Spacers 105 may be formed over both sidewalls of the first conductivestructure 104. The spacers 105 may include an insulating material. Thespacers 105 may include oxide or nitride. The spacers 105 together withthe air gap 110, may function to insulate the first conductivestructures 104 from the second conductive structures 109.

One of the first conductive structure 104 and the second conductivestructure 109 may include a gate and a bit line, and the other of thefirst conductive structure 104 and the second conductive structure 109may include a contact plug, The contact plug may include a storage nodecontact plug, a landing plug, etc. In FIG. 1, the first conductive layer102 of the first conductive structure 104 may include a bit line, andthe second conductive structure 109 may include a storage node contactplug. Accordingly, the air gap 110 may be formed between the bit lineand the storage node contact plug. The storage node contact plug mayhave a structure including the second conductive layer 106, the ohmiccontact layer 107, and the third conductive layer 108. The secondconductive layer 106 may become a first plug, the third conductive layer108 may become a second plug, and the ohmic contact layer 107 is formedbetween the first plug and the second plug. Since the first plugincludes a silicon-containing layer and the second plug includes ametal-containing layer, the storage node contact plug may have a stackstructure including the silicon-containing plug and the metal-containingplug.

As shown in FIG. 1, the air gap 110 is formed between the firstconductive structure 104 and the second conductive structure 109, Theair gap 110 has a dielectric constant of 1 and reduces parasiticcapacitance between the first conductive structure 104 and the secondconductive structure 109. Furthermore, the top of the air gap 110 issealed by the capping layer 111.

The capping layer 111 for capping the air gap 110 is made of oxidegenerated by oxidizing the second conductive layer 106. The passivationlayer 112 is formed over the capping layer 111. Accordingly, the air gap110 may be stably capped. The passivation layer 112 may include siliconnitride. The passivation layer 112 is formed over the capping layer 111and may be formed over the sidewalls of the ohmic contact layer 107 andthe third conductive layer 108.

FIGS. 2A to 2K show cross-sectional views showing a method of forming asemiconductor device in accordance with an embodiment of the presentinvention.

As shown in FIG. 2A, a plurality of first conductive structures 24 isformed over a substrate 21. The substrate 21 may contain silicon (Si).The substrate 21 may include a Si or a silicon germanium (SiGe)substrate. Furthermore, the substrate 21 may include a silicon oninsulator (SOI) substrate.

The first conductive structures 24 formed over the substrate 21 may havea line type in which the first conductive structures 24 are regularlyarranged at regular intervals. Each of the first conductive structures24 includes a first conductive layer pattern 22 and a hard mask pattern23. The method for forming the first conductive structures 24 isdescribed as follows. First, a first conductive layer (not shown) isformed over the substrate 21, and the hard mask pattern 23 is formedover the first conductive layer. Then, the first conductive layerpatterns 22 are formed by etching the first conductive layer by usingthe hard mask pattern 23 as an etch mask. The first conductivestructures 24 in each of which the first conductive layer pattern 22 andthe hard mask pattern 23 are stacked are formed. Each of the firstconductive layer patterns 22 may include a silicon-containing layerand/or a metal-containing layer. For example, the first conductive layerpattern 22 may include a polysilicon layer or a tungsten layer.Furthermore, the first conductive layer pattern 22 may be formed bystacking the polysilicon layer and the metal layer. In this case, abarrier layer may be further formed between the polysilicon layer andthe metal layer. The first conductive layer patterns 22 may have a stackstructure including a polysilicon layer, a titanium-containing layer, ora tungsten layer. The titanium-containing layer is the barrier layer andmay be formed by stacking a Ti layer and a titanium nitride layer.

As shown in FIG. 2B, an insulation layer 25A is formed over the entiresurface including the first conductive structures 24. The insulationlayer 25A may include nitride or oxide. The insulation layer 25A mayinclude silicon nitride and/or silicon oxide. The insulation layer 25Aincludes a material that becomes a spacer.

A sacrificial layer 26A is formed over the insulation layer 25A. Thesacrificial layer 26A includes a material that is removed in asubsequent process and that forms an air gap. The sacrificial layer 26Aincludes a material having an etch selectivity to the insulation layer25A. The sacrificial layer 26A may include oxide, nitride, or metalnitride. If the insulation layer 25A includes oxide, the sacrificiallayer 26A may include metal nitride or nitride. If the insulation layer25A includes nitride, the sacrificial layer 26A may include oxide ormetal nitride. The sacrificial layer 26A may include silicon oxide,silicon nitride, or titanium nitride (TiN).

As shown in FIG. 2C, dual spacers are formed over both sidewalls of thefirst conductive structure 24. The dual spacers include a spacer 25 anda sacrificial spacer 26. The spacer 25 is formed by etching theinsulation layer 25A. The sacrificial spacer 26 is formed over thesidewall of the spacer 25. The sacrificial spacer 26 may be formed byetching the sacrificial layer 26A. In order to form the spacer 25 andthe sacrificial spacer 26, an etch-back process may be performed.

An open part 27 through which the substrate 21 is exposed is formedbetween the first conductive structures 24 because the spacers 25 andthe sacrificial spacers 26 are formed as described above. After formingthe spacers 25, an interlayer insulation layer (not shown) may be formedand the open parts 27 may be formed by etching the interlayer insulationlayer. After forming the open parts 27, the sacrificial spacers 26 maybe formed over the sidewalls of the open parts 27.

The open part 27 may be formed while the sidewalls of the sacrificialspacers 26 are exposed to the open part 27, The open part 27 may have aline type or a contact hole type. For example, if the first conductivestructure 24 includes a bit line structure, the open part 27 may includea storage node contact hole.

As shown in FIG. 2D, a second conductive layer 28A for gap-filling theopen parts 27 is formed. The second conductive layer 28A may include asilicon-containing layer. The second conductive layer 28A may include apolysilicon layer.

As shown in FIG. 2E, the second conductive layer 28A is selectivelyremoved. Accordingly, a second conductive layer pattern 28 is recessedbetween the first conductive structures 24. In order to form the secondconductive layer patterns 28, an etch-back process may be performed. Thesecond conductive layer pattern 28 has a surface that has been recessedlower than a surface of the first conductive structure 24. The recessedsurface of the second conductive layer pattern 28 may be controlled sothat it is higher than at least the top surface of the first conductivelayer pattern 22. The second conductive layer pattern 28 may have aheight that may minimize an area where the second conductive layerpattern 28 faces the first conductive layer pattern 22. Thus, parasiticcapacitance between the first conductive layer pattern 22 and the secondconductive layer pattern 28 may be reduced. The second conductive layerpatterns 28 may become contact plugs. If the first conductive structure24 includes a bit line structure, the second conductive layer pattern 28may become a part of a storage node contact plug. When forming thesecond conductive layer patterns 28, the spacers 25 and the sacrificialspacers 26 are not etched owing to selectivity.

As shown in FIG. 2F, the sacrificial spacers 26 are selectively removed.Accordingly, air gaps 29 are formed. The air gaps 29 may be formed overthe sidewalls of the second conductive layer patterns 28. The air gap 29is formed between the second conductive layer pattern 28 and the firstconductive layer pattern 22. The insulating structure of the ‘air gap29-spacer 25’ is formed between the first conductive layer pattern 22and the second conductive layer pattern 28.

In order to remove the sacrificial spacers 26, wet etch or dry etch maybe performed. When removing the sacrificial spacers 26, the spacers 25,the second conductive layer patterns 28, and the hard mask patterns 23are not damaged owing to selectivity. If the sacrificial spacers 26 are:made of titanium nitride, wet cleaning using a mixed solution of H₂SO₄and H₂O₂ may be performed.

When the air gaps 29 are formed as described above parasitic capacitancebetween the first conductive layer pattern 22 and the second conductivelayer pattern 28 is reduced.

As shown in FIG. 2G, capping layers 30A are formed over the top surfacesand sidewalls of the second conductive layer patterns 28. The cappinglayer 30A may include an insulating material. The capping layer 30A mayinclude the oxide of the second conductive layer pattern 28. The cappinglayer 30A may include silicon oxide, The capping layer 30A may be formedby an oxidization process. Since the second conductive ayer pattern 28includes a silicon-containing layer, silicon oxide may be formed overthe top surfaces and sidewalls of the second conductive layer patterns28 by way of the oxidization process. The capping layer 30A may beformed to a thickness that does not gap-fill the air gap 29. The cappinglayer 30A may be formed by a plasma oxidization method. In this case,the capping layer 30A is formed to a thin thickness that does notgap-fill the air gap 29. If the capping layer 30A is formed by theplasma oxidization method, the capping layer 30A is oxidized on the topsurface of the second conductive layer pattern 28 and at the same timethe capping layer 30A is rapidly oxidized at the top corners of thesecond conductive layer pattern 28. That is, the capping layer 30Aformed over the top corners of the second conductive layer pattern 28has a thickness greater than that of the capping layer 30A formed overthe top surface of the second conductive layer pattern 28. Accordingly,since oxidization is rarely generated on the sidewalls of the secondconductive layer pattern 28, the capping layer 30A that covers thesecond conductive layer pattern 28 may be selectively formed.

When the capping layers 30A are formed the air gaps 29 may be preventedfrom being open in a subsequent process.

As shown in FIG. 2H, a spacer material 31A is formed over the entiresurface in which the capping layers 30A are formed. The spacer material31A may inc ude an insulating material. The spacer material 31A mayinclude silicon nitride. Silicon nitride may be formed by a low pressurechemical vapor deposition (LPCVD) method or a plasma-enhanced chemicalvapor deposition (PECVD) method.

As shown in FIG. 21, the spacer material 31A is selectively removed.Accordingly, passivation layers 31, each having a spacer type, areformed. After forming the passivation layers 31, the capping layers 30Amay be selectively etched so that the second conductive layer patterns28 are exposed. As a result, capping layer patterns 30, which expose thetop surfaces of the second conductive layer patterns 28 and cap the airgaps 29, and the passivation layers 31, which cover the upper sides andsidewalls of the open parts over the capping layer patterns 30, areformed. When etching the spacer material, the air gaps 29 may beprevented from being opened because the capping, layer patterns 30function as etch barriers.

In another embodiment, after forming the capping layers 30A, the cappinglayers 30A may be selectively etched so as to form the capping layerpatterns 30 which expose the top surfaces of the second conductive layerpatterns 28 and cap the air gaps 29. Then, after forming the spacermaterial 31A, the spacer material 31A is selectively removed so as toform the passivation layers 31 which cover the upper sides and sidewallsof the open parts over the capping layer patterns 30. Accordingly, whenetching the spacer materials the air gaps 29 may be prevented from beingopened because the capping layer patterns 30 function as etch barriers.

Although not shown, voids generated within the first conductive layerpatterns 28 may be removed by performing rapid thermal annealing (RTA)after forming the passivation layers 31. Furthermore, after the RTA, ionimplantation may be performed as a subsequent process. The ionimplantation is performed in order to improve contact resistance.

As shown in FIG. 2J, ohmic contact layers 32 are formed over the secondconductive layer patterns 28, respectively. The ohmic contact layer 32may include metal silicide. In order to form metal silicide, annealingmay be performed after forming a metal layer (not shown) on the entiresurface. The metal layer may include a material that may be silicidized.The metal layer may include cobalt (Co). Metal silicide may be formedbecause the metal layer reacts to the silicon of the second conductivelayer pattern 28 by way of the annealing. The metal silicide may includecobalt silicide. In the present embodiment the metal silicide mayinclude cobalt silicide having a ‘CoSi₂ phase’.

Since cobalt silicide having a CoSi₂ phase is formed as the ohmiccontact layer 32, contact resistance may be improved and cobalt silicidehaving sufficient low resistance even in the small area of the open part27 having a fine line width may also be formed.

Next, a non-reacted metal layer is stripped. If the non-reacted metallayer is not removed, the metal atoms of the non-reacted metal layer maybe diffused downward or the metal atoms of the non-reacted metal layermay generate an abnormal reaction with a metal silicide layer 32 in asubsequent process. For this reason, the non-reacted metal layer isremoved. The non-reacted metal layer may be removed by a cleaningprocess using wet chemicals. For example, if the non-reacted metal layeris cobalt (Co) the non-reacted metal layer may be removed by H₂SO₄ (SPM)and NH₄OH (SC-1)-series chemicals. Incidentally, the non-reacted metallayer may be oxidized using deionized (DI) water and may be primarilyremoved using H₂SO₄ (SPM), and metallic polymer-series residues may besecondarily removed using NH₄OH-series chemicals.

If the wet chemicals are used as described above, both the non-reactedmetal layer and metallic polymer may be removed cleanly.

Meanwhile, in order to form cobalt silicide, RTA may be performed atleast twice. For example, primary annealing and secondary annealing maybe performed. The primary annealing may be performed in a temperature of400˜600V, and the secondary annealing may be performed in a temperatureof 600˜800° C. Cobalt silicide having a ‘CoSi_(x) (x=0.1˜1.5) phase’ isformed by the primary annealing. The cobalt silicide having a ‘CoSi_(x)(x=0.1˜1.5)’ phase is changed into cobalt silicide having a ‘CoSi₂phase’ by way of the secondary annealing. From among cobalt silicides,cobalt silicide having a ‘CoSi₂ phase’ has the lowest resistivity.Non-reacted cobalt is removed between the primary annealing and thesecondary annealing. The non-reacted cobalt may be removed using mixedchemicals of sulfuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂).

As shown in FIG. 2K, third conductive layer patterns 33 are formed overthe ohmic contact layers 32. In order to form the third conductive layerpatterns 33, a polishing process may be performed after forming a thirdconductive layer that gap-fills the top surfaces of the ohmic contactlayers 32. The third conductive layer pattern 33 to may include ametal-containing layer. The third conductive layer pattern 33 mayinclude a tungsten layer. Although not shown, the third conductive layerpattern 33 may further include a barrier layer. Accordingly, the thirdconductive layer pattern 33 may be formed by stacking the barrier layerand the metal-containing layer. The barrier layer may include a materiaicontaining titanium (Ti). The barrier layer may be made of titanium (Ti)solely or may be formed by stacking titanium (Ti) and titanium nitricle(TiN). If the third conductive layer pattern 33 includes a material thatdoes not react to the second conductive layer pattern 28, the barrierlayer may be omitted.

If the third conductive layer patterns 33 are formed as described above,second conductive structures 34 each including the second conductivelayer pattern 28, the ohmic contact layer 32, and the third conductivelayer pattern 33 are formed. The air gap 29 is formed between the firstconductive structure 24 and the second conductive structure 34. Thesecond conductive structure 34 may become a storage node contact plug.The second conductive layer pattern 28 may become the bottom plug of thestorage node contact plug, and the third conductive layer pattern 33 maybecome the top plug of the storage node contact plug. Since the secondconductive layer pattern 28 includes the silicon-containing layer andthe third conductive layer pattern 33 includes the metal-containinglayer, a contact plug including the silicon-containing layer and themetal-containing layer, that is, a semi-metal contact plug structure,may be formed.

The air gap 29 may be formed between the first conductive layer pattern22 and the second conductive layer pattern 28. If the first conductivelayer pattern 22 includes a bit line and the second conductive layerpattern 28 includes a storage node contact plug, the air gap 29 may beformed between the bit line and the storage node contact plug. If thefirst conductive layer pattern 22 includes a gate electrode and thesecond conductive layer pattern 28 includes a contact plug, the air gap29 may be formed between the gate electrode and the contact plug.

FIGS. 3A and 3B illustrate comparative examples that are compared withthe present embodiment.

Referring to FIGS. 3A and 3B, a plurality of first conductive structures44 in each of which a first conductive layer 42 and a hard mask layer 43are stacked is formed over a substrate 41, and a second conductive layer46 that forms a second conductive structure is formed between the firstconductive structures 44. An air gap 47 is formed between the firstconductive structure 44 and the second conductive layer 46. Spacers 45are formed over the sidewalls of the first conductive structure 44.

In the comparison examples, a single insulating material may be used asa capping layer 48. The capping layer 48 may include silicon nitride orsilicon oxide. When an insulating material is used as the capping layer48, the capping layer 48 has to be selectively removed from a surface ofthe second conductive layer 46 for a subsequent process.

If the capping layer 48 is attacked by a subsequent process, however, aself-alignment contact (SAC) fail is generated. If the capping layer 48is thickly formed in order to form stable air gaps 47, contactresistance may be greatly increased because an area where metal silicideis formed may be greatly reduced.

In particular, if the capping layer 48 is solely formed there is aproblem in that the air gaps 47 are opened because the capping layer 48is attached when etching the capping layer 48 in order to form metalsilicide by opening the top surfaces of the second conductive layers 46(refer to reference numeral 49).

As a result, as in the present embodiment, when the air gap 29 is cappedwith the dual structure of the capping layer pattern 30 and thepassivation layer 31 using silicon nitride by way of a plasmaoxidization process, a top-open margin may be secured and the air gapmay also be sufficiently capped.

FIG. 4A shows memory cells of DRAM, FIG. 4B is a cross-sectional view ofthe DRAM taken along line A-A′ of FIG. 4A, and FIG. 4C is across-sectional view of the DRAM taken along line B-B′ of FIG. 4A.

Referring to FIGS. 4A, 4B, and 4C, active regions 53 are defined in asubstrate 51 by way of isolation regions 52. Burial gate electrodes 56are formed in respective trenches 54 that cross the active regions 53and the isolation regions 52. Bit lines 61 extended in a direction tocross the burial gate electrodes 56 are formed over the substrate 51,and the bit lines 61 are connected to the active regions 53 throughrespective bit line contact plugs 60. Storage node contact plugsconnected to the respective active regions 53 are formed. Each of thestorage node contact plugs may be formed by stacking a first plug 66, anohmic contact layer 70, and a second plug 71. The storage node 72 of acapacitor is formed over each of the second plugs 71 of the storage nodecontact plugs.

The storage node contact plug may correspond to the second conductivestructure according to the present embodiments, and the bit line maycorrespond to the first conductive layer pattern of the first conductivestructure according to the present embodiments. Accordingly, the air gap67 may be formed between the storage node contact plug and the bit line61. The storage node contact plug may include the first plug 66 and thesecond plug 71 and may further include the ohmic contact layer 70 formedbetween the first plug 66 and the second plug 71. The ohmic contactlayer 70 may include metal silicide, such as cobalt silicide.

The air gap 67 is capped with a capping layer 68, and a passivationlayer 69 is formed over the capping layer 68. The capping layer 68 andthe passivation layer 69 may correspond to the capping layer accordingto the present embodiments. Accordingly, the capping layer 68 mayinclude silicon oxide, and the passivation layer 69 may include siliconnitride.

A method of fabricating the memo cells is described below with referenceto FIGS. 4A, 4B, and 4C.

The substrate 51 includes a semiconductor material. The substrate 51 mayinclude a semiconductor substrate. The substrate 51 may include asilicon substrate and may include, for example, a ngle crystallinesilicon substrate. The isolation regions 52 may be formed by a shallowtrench isolation (STI) process. The active regions 53 are defined by theisolation regions 52. The isolation regions 52 may be formed bysequentially stacking wall oxide, a liner, and a gap-fill material. Theliner may include silicon nitride and silicon oxide. The silicon nitridemay include Si₃N₄, and the silicon oxide may include SiO₂. The gap-fillmaterial may include silicon oxide, such as a spin-on insulator (SOD).Furthermore, the gap-fill material may include silicon nitride. In thiscase the silicon nitride may be gap-filled using silicon nitride used asa liner.

The trenches 54 are formed in the active regions 53 and the isolationregions 52 at the same time. The trench 54 may be formed deeper in theisolation region 52 than in the active region 53 because of a differencebetween the etch rates of the active region 53 and the isolation region52.

Prior to the formation of the burial gate electrodes 56, a gateinsulation layer 55 may be formed over surfaces of the trenches 54. Theburial gate electrodes 56 are formed by forming a metal containing layerso that the trenches 54 are gap-filled and then performing an etch-back.The metal-containing layer may include a material including metal, suchas titanium (Ti), tantalum (Ta), or tungsten (W), as a major ingredient.The metal-containing layer may include any one selected from the groupconsisting of tantalum nitride (TaN), titanium nitride (TiN), tungstennitride (WN), and tungsten (W). For example, the burial gate electrode56 may include TiN, TaN, or W solely or may have a dual-layer layer,such as TiN/W or TaN/W in which W is stacked on TiN or TaN. Furthermore,the burial gate electrode 56 may include a dual-layer layer, such WN/Win which W is stacked on WN. In addition, the burial gate electrode 56may include a metal material having low resistance.

A sealing layer 57 is formed over the burial gate electrodes 56. Thesealing layer 57 may gap-fill the trenches 54 on the burial gateelectrodes 56. The sealing layer 57 may function to protect the burialgate electrode 56 in a subsequent process. The sealing layer 57 mayinclude an insulating material. The sealing layer 57 may include siliconnitride.

After forming the first interlayer insulation layer 58, bit line contactholes 59 are formed by etching the first interlayer insulation layer 58and the sealing layer 57. The bit line contact plugs 60 are formed byforming a conductive layer in the bit line contact holes 59. Bit linestructures, each including the bit line 61 and a bit line hard masklayer 62, are formed over the respective bit line contact plugs 60. Thebit line contact plug 60 may include a polysilicon layer or ametal-containing layer. The bit line 61 may include a tungsten layer andmay include a barrier layer, such as Ti/TiN, and a tungsten layer on thebarrier layer. The bit line hard mask layer 62 may include siliconnitride.

Spacers 63 are formed over both sidewalls of each of the bit linestructures. Next, after forming a second interlayer insulation layer 64,storage node contact holes 65 are formed by etching the secondinterlayer insulation layer 64, the first interlayer insulation layer58, and the sealing layer 57. After forming sacrificial spacers (notshown) on the sidewalls of the storage node contact holes 65, the firstplugs 66 recessed in the storage node contact holes 65 are formed. Theair gaps 67 are formed by removing the sacrificial spacers.

Next, the capping layers 68 are formed by oxidizing the surfaces of thefirst plugs 66, and the capping layers 68 are selectively removed sothat the surfaces of the first plugs 66 are exposed. This process may beperformed after an etch-back process for forming the passivation layers69. The air gaps 67 are capped with the respective capping layers 68.The passivation layer 69 protects the capping layer 68.

After forming the ohmic contact layers 70 on the first plugs 66 by usingmetal silicide, the second plugs 71 are formed over the respective ohmiccontact layers 70. The second plug 71 may include a metal-containinglayer. The second plug 71 may include a tungsten layer. Although notshown, the second plug 71 may further include a barrier layer.Accordingly, the second plug 71 may have a stack structure including thebarrier layer and the metal-containing layer. The barrier layer mayinclude a material including titanium (Ti). The barrier layer may bemade of titanium (Ti) solely or may be formed by stacking titanium (Ti)and titanium nitride (TiN).

The storage node 72 of a capacitor is formed over the second plug 71.The storage node 72 may have a cylinder type and may have a pillar typein other embodiments. Although not shown, a dielectric layer and a platenode may be further formed over the storage node 72.

The semiconductor device according to the aforementioned embodiments maybe applied to dynamic random access memory (DRAM), but is not limitedthereto. The semiconductor device may be applied to static random accessmemory (SRAM), flash memory, ferroelectric random access memory (FeRAM),magnetic random access memory (MRAM), and phase change random accessmemory (PRAM), for example.

FIG. 5 is a schematic diagram of a memory card.

Referring to FIG. 5, the memory card 200 may include a controller 210and memory 220. The controller 210 and the memory 220 may exchangeelectric signals. For example, the memory 220 and the controller 210 mayexchange data in response to an instruction from the controller 210.Accordingly, the memory card 200 may store data in the memory 220 orexternally output data from the memory 220. The memory 220 may includeair gaps and plugs, such as those described above. The memory card 200may be used as a variety of data storage media for a variety of handhelddevices. For example the memory card 200 may include a memory stickcard, a smart media (SM) card, a secure digital (SD) card, a mini-securedigital (mini SD) card or a multi-media card (MMC), etc.

FIG. 6 is a block diagram of an electronic system.

Referring to FIG. 6, the electronic system 300 may include a processor310, an I/O device 330, and a chip 320. The processor 310, the I/Odevice 330, and the chip 320 may communicate data with each other byusing a bus 340. The processor 310 may function to execute a program andcontrol the electronic system 300. The I/O device 330 may be used toinput or output the data of the electronic system 300. The electronicsystem 300 may be connected to an external device, for example, apersonal computer or a network through the I/O device 330 and mayexchange data with the external device. The chip 320 may store a codeand data for the operation of the processor 310 and process part of anoperation assigned by the processor 310. For example, the chip 320 mayinclude air gaps and plugs, such as those described above. Theelectronic system 300 may form a variety of electronic control devicesthat require the chip 320. For example, the electronic system 300 may beused in mobile phones, MP3 players, navigators, solid state disks(SSDs), and household appliances.

This technology has an advantage in that it may reduce parasiticcapacitance due to the air gap having a low dielectric constant becausethe air gap is formed between the conductive structures.

Furthermore this technology is advantageous in that the air gap may bepreven ted from being opened in a subsequent process because thepassivation layer is formed over the capping layer that caps the air gapand thus the air gap may be stably capped.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1-14. (canceled)
 15. A semiconductor device comprising: a plurality ofbit line structures formed over a substrate; storage node contact holesformed to have sidewalls of the bit line structures exposedtherethrough; silicon plugs recessed and formed in the respectivestorage node contact holes; air gaps formed between the sidewalls of thebit line structures and the silicon plugs; capping layer patterns formedover the air gaps; passivation layers formed over the respective cappinglayer patterns; and metal plugs formed over the respective siliconplugs, wherein the air gaps are capped with the respective capping layerpatterns and passivation layers.
 16. The semiconductor device of claim15, wherein the capping layer patterns comprise oxide of the siliconplugs.
 17. The semiconductor device of claim 15, wherein the passivationlayers are formed of a spacer type, which covers upper sides andsidewalls of the storage node contact holes.
 18. The semiconductordevice of claim 15, wherein the passivation layers comprise siliconnitride.
 19. The semiconductor device of claim 15, wherein: each siliconplug comprises a polysilicon layer, and each metal plug comprises atungsten layer.
 20. The semiconductor device of claim 15, furthercomprising: metal silicide formed between the silicon plugs and themetal plugs.